High performance phase-locked loops (PLLs) are widely used in digital microprocessors, wireline/optical links, and data converters, among many other applications. In the meantime, an increasing number of PLLs are demanded and integrated on a single System-on-Chip for such applications. Therefore, it becomes imperative to design area efficient PLLs while without sacrificing their phase noise (PN) or jitter performance. Ring oscillator (RO)-based PLLs are extremely compact and can generate multiple output phases with wide frequency tuning range. However, the intrinsic high RO PN renders the implementation of RO-based PLLs with a low power consumption and a low PN extremely challenging. In this talk, we will go through popular techniques to suppress RO PN for compact PLL design, along with a few newly proposed methods that achieve state-of-the-art jitter performance with a small area consumption.
BIO of SPEAKER:Hui Wang (Senior Member, IEEE) received the B.Sc. degree in Microelectronics from Shanghai Jiao Tong University, Shanghai, China, and the Ph.D. degree in Electrical and Computer Engineering from the University of California at San Diego (UCSD), La Jolla, CA, USA, respectively.
He is currently an Associate Professor with the School of Integrated Circuits at Shanghai Jiao Tong University (SJTU), Shanghai, China. His research focuses on high-performance wireline and wireless integrated circuits design, including high-speed SerDes/IOs, high-speed energy-efficient RF transceivers, energy-efficient power management, and high-performance frequency synthesizers. Prior to joining Shanghai Jiao Tong University, Prof. Wang was a postdoctoral scholar with Stanford University, Stanford, CA, USA, where he researched fully integrated high throughput wireless transceivers, and worked at Qualcomm Technologies Inc. (QCT), Santa Clara, CA, USA, developing high-performance radio-frequency and analog integrated circuits. Prof. Wang serves as a Guest Editor of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI). He is currently a member of the IEEE Custom Integrated Circuits Conference (CICC) technical program committee.
BIO of SPEAKER:Hui Wang (Senior Member, IEEE) received the B.Sc. degree in Microelectronics from Shanghai Jiao Tong University, Shanghai, China, and the Ph.D. degree in Electrical and Computer Engineering from the University of California at San Diego (UCSD), La Jolla, CA, USA, respectively.
He is currently an Associate Professor with the School of Integrated Circuits at Shanghai Jiao Tong University (SJTU), Shanghai, China. His research focuses on high-performance wireline and wireless integrated circuits design, including high-speed SerDes/IOs, high-speed energy-efficient RF transceivers, energy-efficient power management, and high-performance frequency synthesizers. Prior to joining Shanghai Jiao Tong University, Prof. Wang was a postdoctoral scholar with Stanford University, Stanford, CA, USA, where he researched fully integrated high throughput wireless transceivers, and worked at Qualcomm Technologies Inc. (QCT), Santa Clara, CA, USA, developing high-performance radio-frequency and analog integrated circuits. Prof. Wang serves as a Guest Editor of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI). He is currently a member of the IEEE Custom Integrated Circuits Conference (CICC) technical program committee.
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