Six papers from ShanghaiTech University’s School of Information Science and Technology (SIST) were accepted to the 63rd Design Automation Conference (DAC 2026), held in Long Beach, California. DAC is one of the oldest and most influential conferences in electronic design automation (EDA).
DAC has increasingly spotlighted a two-way trend: artificial intelligence (AI) is helping engineers design and manufacture chips faster and more accurately, while chip-design methods, in turn, are helping build more efficient hardware for AI itself. Of the six papers, three focus on using AI to speed up chip design, while the other three focus on using chip-design thinking to make AI hardware more efficient.
AI for EDA
Scanning chip layouts 407 times faster
When designing a chip, engineers often need to search for a specific target pattern—say, a geometric structure known to cause manufacturing defects—across an entire circuit layout that can contain hundreds of millions of shapes, to check whether the design meets manufacturing rules. The larger and more complex the layout, the more time and computing power this search consumes.
G-Matcher, a pattern-matching system built specifically for GPUs, was developed to handle the bottleneck. It organizes massive layout data into a multi-level hierarchy, then uses multiple rounds of filtering to progressively rule out irrelevant regions, dramatically speeding up the search. Tested on a real industrial layout containing more than 100 million shapes, G-Matcher ran 407 times faster on average than Calibre, an industry-standard tool running on a 64-core processor—while maintaining 100 percent accuracy and zero false positives across every test case. The tool could make critical steps in chip design and manufacturing verification both faster and more reliable.
Co-first authors: 2024 master’s students Wang Nan and Dong Hanbin
Co-corresponding authors: Chair Professor Yu Jingyi and Assistant Professor Geng Hao
Making lithography simulation both faster and more accurate
Chip manufacturing relies on photolithography to “print” circuit patterns onto silicon. Simulating this process accurately allows engineers to catch and fix problems before production begins, saving significant time and cost. But existing simulation methods typically force a trade-off: either they are accurate but slow, or fast but less precise.
The SIST’s new framework, N3Litho, combines numerical computation with neural networks. Using optical field data captured at the image plane, together with parameters describing the 3D mask and film stack, it reconstructs the three-dimensional optical field inside the photoresist—achieving high simulation accuracy without the heavy computational cost of solving the full physics from scratch. In tests, N3Litho’s accuracy came close to that of rigorous physics-based simulation while outperforming existing learning-based methods, and it ran an order of magnitude faster. Its output can feed directly into downstream tasks such as photoresist modeling, lithography pattern optimization, and detection of manufacturing “hotspots” that could compromise chip quality.
Co-first authors: 2025 PhD student Chen Yuyang and 2024 master’s student Wang Zhen
Co-corresponding authors: Chair Professor Yu Jingyi and Assistant Professor Geng Hao
Co-optimizing light source and mask to widen the margin for error
In photolithography, both the light source and the “mask” (the pattern template) affect whether a chip can be manufactured reliably. The two need to be optimized together so that a design still comes out correctly even when manufacturing conditions fluctuate slightly. Traditional methods, however, are computationally expensive and typically optimize only one source-mask pairing at a time through repeated iterations—a slow, inefficient process.
The team’s new method, CPW-SMO, optimizes a single shared light source together with an entire set of masks at once, allowing multiple different patterns to achieve a wider “process window”—the margin of manufacturing variation a design can tolerate—under the same source. The method reframes what is normally a complex, hard-to-solve multi-objective problem into a more tractable form, then uses highly parallelized lithography simulation to speed up the calculation. Experiments showed the approach significantly widens the process window while also cutting optimization time, and it shows promise for use across a complete lithography workflow.
First author: 2023 master’s student He Hongquan
Co-corresponding authors: Chair Professor Yu Jingyi and Assistant Professor Geng Hao
EDA for AI
Predicting an AI chip’s power use—in seconds—from its compiler
AI accelerators—the specialized chips that run neural networks in data centers and edge devices—need accurate power estimates as early as possible in the design process, so engineers can adjust the hardware before problems surface late in development.
The researchers found a new source of insight: the compilation step. Before a neural network can run on an AI accelerator, it must first be compiled—mapped and scheduled onto the underlying hardware. That process determines exactly how computation and data movement happen, and so it already contains rich information about power consumption. Building on this insight, the researchers designed a two-stage learning model that predicts both average power and total energy use simultaneously.
In testing, the method’s predictions were more accurate than existing state-of-the-art approaches across two major accelerator-generation frameworks, and it generalized well even to larger, previously unseen network architectures. Each prediction takes only seconds, making it a fast, practical tool for evaluating and optimizing AI chip energy use during the design phase.
First author: 2025 PhD student Luo Dong’er
Corresponding author: Assistant Professor Geng Hao
A string of “structured randomness” that cuts an AI chip’s power use
AI computation depends on huge numbers of multiplications and matrix operations, and how those operations are implemented in hardware directly determines a chip’s power consumption and size. “Stochastic computing” offers an alternative approach: it can perform multiplication and other operations using much simpler logic circuits, reducing hardware overhead. But in conventional implementations, to generate the random bitstreams, the method relies on extra circuitry—overhead that eats into the very savings stochastic computing is supposed to deliver.
The proposed new architecture, ALOHA, takes a different approach: it replaces the traditional random-bitstream generator with a “Hammersley sequence”—a deterministic, mathematically defined sequence that is highly uniform in its distribution. Because the sequence follows a fixed rule rather than true randomness, it can be generated efficiently using just simple counters and rewired logic. The team paired this with additional circuit-level optimizations to eliminate unnecessary computation steps. In tests, ALOHA achieved significantly lower circuit area and power consumption than existing designs for multiplication and matrix-multiplication tasks. When it was applied to convolutional neural networks and vision Transformer models, the accuracy loss stayed within 0.5 percent.
First author: 2024 PhD student Ni Zhaojun
Corresponding author: Assistant Professor Liu Siting
Computing with light instead of electricity cuts energy use by more than half
As AI models keep growing, the energy and speed limits of conventional computing hardware are becoming harder to ignore—pushing researchers to explore doing part of the computation with light instead of electricity. Microring resonators are a promising building block for optical AI chips: they are compact, switch quickly, and can process multiple signals in parallel by using different wavelengths of light at once, a technique known as wavelength-division multiplexing. But optical computing has a persistent bottleneck: light signals must repeatedly be converted to electrical signals and back again between computing steps, and that conversion process itself consumes significant time and energy.
The team’s new architecture, ROSA, uses optical beam splitters and delay lines to perform “shift-and-add” operations directly within the optical domain—scaling, aligning, and adding together partial results computed at different points in time, all in light, without converting them to electrical signals first. This cuts down on the overhead from optical-to-electrical conversion and intermediate data access. Experiments showed that, compared with existing approaches, ROSA reduced its energy-delay product—a combined measure of energy efficiency and speed—by 54.7 percent on average, pointing to a new path toward more energy-efficient optical AI accelerators.
First author: Class of 2026 PhD graduate Zhang Huifan
Co-corresponding authors: Assistant Professor Qu Yurui and Professor Zhou Pingqiang